1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and method for testing the semiconductor device and in particular to the semiconductor testing apparatus capable of resuming a control sequence from a predetermined address after the control sequence for a test is once stopped.
2. Description of the Related Art
FIG. 1 is a block diagram showing the structure of a pattern generator 10 in a typical semiconductor device testing apparatus. The pattern generator 10 is comprised of a match-fail detecting unit 20, a sequence control unit and a pattern data memory 50. Each component of the pattern generator 10 is controlled by a control unit 210, and receives a clock signal output from a reference clock generator 60.
The semiconductor device testing apparatus is used for testing logic ICs such as a system LSI, and can test a plurality of semiconductor devices simultaneously.
The pattern generator 10 generates, according to a predetermined control sequence, an input signal pattern that is to be input to a semiconductor device under test, and an expectation data pattern 14 that is expected to be output from the semiconductor device in the event that the input signal pattern 12 is input to the semiconductor device.
The input signal pattern 12 and the expectation data pattern 14 are stored in a pattern data memory 50. The sequence control unit 40 outputs an address signal 45 to the pattern data memory 50 so as to generate the input signal pattern 12 and the expectation data signal pattern 14. Moreover, the sequence control unit 40 receives a match signal 96 indicating whether or not the output signal pattern output from the semiconductor device is matched with a desired value determined based on the expectation data signal pattern 14. The match-fail detecting unit 20 outputs to the sequence control unit 40 a match-fail signal 22 when the match-fail detecting unit 20 does not receive the match signal 96 during a match cycle waiting for the match signal 96.
The sequence control unit 40 is comprised of a pattern counter 42, an address counter 44 and a control sequence, and a controller 46. The pattern counter 42 counts a match cycle while the address counter 44 counts the address of the control sequence. The controller 46 controls the pattern counter 42 and the address counter 44 according to a predetermined control sequence, and outputs a match cycle signal indicating of being in the midst of match cycle, to the match fail detecting unit 20, and receives the match-fail signal 22 output from the match-fail detecting unit 20. Moreover, upon receipt of the match-fail signal 22 the controller 46 outputs a clock control signal 48 serving to stop generation of clock signals by the reference clock generator 60.
When the controller 46 receives the match signal 96 during the match cycle, the controller 46 controls the pattern counter 42 and the address counter 44 so as to continue the control sequence. On the other hand, upon receipt of the match-fail signal 22 the controller 46 controls the pattern counter 42 and the address counter 44 so that the control sequence is stopped, and performs a fail stop process so as to output the clock control signal 48. The testing is stopped by the fail stop process, thus the testing has to be started over in order to resume the test.
When testing a plurality of semiconductor devices simultaneously, the test is performed while confirming whether or not the write of the input signal pattern 12 to and readout of the output signal pattern from all the semiconductor devices are properly completed. Therefore, a series of several different types of testing procedures are divided accordingly and the completion of the read-write of each semiconductor device 200 are confirmed during a fixed period of time between these testing procedures called the match cycle (this is called a match performance). When the match is not performed during the match cycle, it means that at least one of the plural semiconductor devices under test is defective, so that the defective device is removed from the test after the test is stopped and thereafter the test will be resumed.
FIG. 2 is a flow chart showing a process of testing a single semiconductor device using the conventional semiconductor device testing apparatus. In a test 1 (S102), the input pattern 12 is input to the semiconductor device. Thereafter, when in the match cycle (S104) the output signal pattern output from the semiconductor device is matched with a desired value determined based on the expectation data signal pattern 14 (that is, when the match is performed), the performance of a test 2 will continue in a sequel. When the output signal pattern is not matched with the desired value (that is, when the match is not performed), the test is terminated at once as being a match fail. The same process is carried out in the match cycle after the test 2 (S106). When a test 3 (S110) is performed, all the test processes are completed.
FIG. 3 is a flow chart showing a process simultaneously testing a plurality of semiconductor devices using the conventional semiconductor device testing apparatus. After performing a test 1 (S152), when a match is performed in the match cycle (S154), a test 2 (S156) will continue. However, when the match is not performed, the test is terminated at once as being the match fail (S162). After the test is stopped, the semiconductor device having caused the match fail is removed from testing objects. Then, when the test is performed on the remaining devices, the test 1 is started all over (S152). If the match is not performed then, the test is terminated. Thereafter, the same process is carried out (S162, S164) in the match cycle (S158) after the test 2 (S156). When a test 3 (S110) is performed, all the test processes are completed.
FIG. 4 is a timing chart of an example compared to the present embodiment, showing a process for simultaneously testing a plurality of semiconductor devices using the semiconductor device testing apparatus. After a test 1 (S202) is performed, the match is performed on a plurality of semiconductor devices in the match cycle (S204). If any single match fail is caused, then the test for all devices are stopped (S206). Thereafter, a semiconductor device having caused the match fail is removed from the testing objects (S208), and the test 1 is started from the outset on the other remaining semiconductor devices (S210). Thereafter, the test 1 (S210), test 2 (S214) and test 3 (S218) are performed in this order, and all testing processes will be completed if no match fail occurs in each match cycle (S212, S216).
In the conventional practice of simultaneously testing a plurality of semiconductor devices, the test of all semiconductor devices is stopped when any single match fail occurs in the semiconductor devices in the match cycle, and then the semiconductor device having caused the match fail is removed from the testing objects. Moreover, in order to complete the test of the remaining semiconductor devices the test has to be started all over from the beginning. Thus, this does not result in reducing the testing time even though a plurality of semiconductor devices are simultaneously tested.
Moreover, in the course of testing the semiconductor device such as a system LSI having a flash memory built therein, a re-start of the test after an temporal stoppage of the test caused by the match fail may lead to an excessive write to the flash memory by as much as the overlapped process of the same testing process, thus possibly damaging the device. As a result, the test may not proceed further.
Moreover, when the semiconductor device such as the system LSI having a built-in PLL device (phase lock loop device) is tested, the PLL need be locked by continuously inputting a clock for a certain period of time prior to the start of the test. Thereby, whenever the test is resumed for the remaining semiconductor devices, waiting time until the PLL is locked is necessary, thus causing difficulty in that the test can not be re-started at once.
Therefore, it is an object of the present invention to provide semiconductor device testing apparatus and method therefor which overcome the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to one aspect of the present invention, there is provided semiconductor device testing apparatus for testing a semiconductor device, comprising: a pattern generator which, based on a predetermined control sequence, generates an input signal pattern that is to be input to the semiconductor device, and an expectation data signal pattern that is expected to be output from the semiconductor device with the input signal pattern having been input to the semiconductor device; a comparison unit which compares an output signal pattern output from the semiconductor device and the expectation data signal pattern, and outputs a match signal in the event that the output signal is matched with predetermined data determined based on the expectation data signal pattern. Moreover, the pattern generator includes: a stoppage unit which stops the control sequence in the event that a match fail in which the match signal does not become active during a predetermined cycle is caused; a resuming address register which sets up a resuming address indicating a resuming position of the control sequence; and a resuming unit which resumes the control sequence based on the resuming address.
The pattern generator may further comprises: a pattern data memory which stores data of the input signal pattern and the expectation data signal pattern; and a sequence control unit which generates the input signal pattern and the expectation data signal pattern by supplying an address signal to the pattern data memory, and stops an output of the address signal and thereafter resumes the output of the address signal based on the resuming address set by the resuming address register in the event of the match fail caused.
Preferably, the sequence control unit includes a fail-hold processing unit for performing a fail-hold process which stops an output of the address signal and an input of the input signal pattern to the semiconductor device in the event of the match fail caused.
Moreover, the sequence control unit may further include a fail-burst processing unit for performing a fail-burst process which stops an output of the address signal and repeatedly supplies the same input signal pattern to the semiconductor device in the event of the match fail caused.
Moreover, the pattern generator may further include a mode selector which selects one among any of a plurality of processes including the fail-hold process and fail-burst process in the event of the match fail caused.
Moreover, the pattern generator may further include a mode register which sets to select a process of said plurality of processes in the event of the match fail caused. Preferably, the mode selector selects a single process among the plurality of processes based on a setting set by the mode register.
Moreover, the semiconductor device testing apparatus may further comprise: a timing generator which generates a timing signal that controls a timing of supplying the input signal pattern to the semiconductor device a waveform shaper which shapes a waveform of the input signal based on the timing signal. Preferably, the fail-hold processing unit stops an input of the input signal pattern to the semiconductor device by stopping the timing signal.
Moreover, the fail-burst processing unit outputs continuously the timing signal, so that the same input signal pattern is repeatedly input to the semiconductor device.
Moreover, the semiconductor device testing apparatus may further comprise: a plurality of semiconductor device contact portions which respectively place a plurality of the semiconductor devices thereon, respectively receive the input signal pattern so as to be supplied to a plurality of the semiconductor devices, and respectively receive the output signal output from a plurality of the semiconductor devices. Preferably, the comparison unit compares each of the output signal patterns output from a plurality of the semiconductor devices with the expectation data signal pattern so as to output the match signal.
According to another aspect of the present invention, there is provided a semiconductor device testing method of testing a semiconductor device, comprising: generating, in accordance with a predetermined control sequence, an input signal pattern to be supplied to the semiconductor device, and an expectation data signal pattern to be output from the semiconductor device after the input signal pattern having been input to the semiconductor device; outputting a match signal in the event that an output signal pattern to be output from the semiconductor device is compared to the expectation signal pattern so that the output signal pattern is matched with a desired value determined based on the expectation data signal pattern; stopping the control sequence in the event that a match fail in which the match signal does not become active during a predetermined match cycle is caused; storing a re-start address which indicates a resuming position of the control sequence; and resuming the control sequence based on the re-start address.
Moreover, the semiconductor device testing method may further comprise: performing a fail-hold process by which to stop the control sequence and an input of the input signal pattern to the semiconductor device in the event that the match fail is caused.
Moreover, the semiconductor device testing method may further comprise: performing a fail-burst process by which to stop the control sequence and to repeatedly input the same input signal pattern to the semiconductor device in the event that the match fail is caused.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination.of these described features.